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| author | Philippe Mathieu-Daudé | 2020-09-03 17:31:04 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2020-10-21 13:19:02 +0200 |
| commit | 9321c1f2d08817fdb90ad129fbe3194207e73ba0 (patch) | |
| tree | ea06c8e85fd45b51d6c739ad6345b70f61c101e2 | |
| parent | hw/sd/sdhci: Let sdhci_update_irq() return if IRQ was delivered (diff) | |
| download | qemu-9321c1f2d08817fdb90ad129fbe3194207e73ba0.tar.gz qemu-9321c1f2d08817fdb90ad129fbe3194207e73ba0.tar.xz qemu-9321c1f2d08817fdb90ad129fbe3194207e73ba0.zip | |
hw/sd/sdhci: Yield if interrupt delivered during multiple transfer
The Descriptor Table has a bit to allow the DMA to generates
Interrupt when the operation of the descriptor line is completed
(see "1.13.4. Descriptor Table" of 'SD Host Controller Simplified
Specification Version 2.00').
If we have pending interrupt and the descriptor requires it
to be generated as soon as it is completed, reschedule pending
transfers and yield to the CPU.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200903172806.489710-5-f4bug@amsat.org>
| -rw-r--r-- | hw/sd/sdhci.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index b93ecefd20..2f8b74a84f 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -837,7 +837,10 @@ static void sdhci_do_adma(SDHCIState *s) s->norintsts |= SDHC_NIS_DMA; } - sdhci_update_irq(s); + if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { + /* IRQ delivered, reschedule current transfer */ + break; + } } /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ |