diff options
| author | Tong Zhang | 2022-09-15 19:59:04 +0200 |
|---|---|---|
| committer | Laurent Vivier | 2022-09-29 21:18:40 +0200 |
| commit | c6cc866c0eaab1deddea21bf0b386730ed71bb97 (patch) | |
| tree | dc40469a0e849438545046d2362af024eeb93d1b | |
| parent | .gitignore: add .cache/ to .gitignore (diff) | |
| download | qemu-c6cc866c0eaab1deddea21bf0b386730ed71bb97.tar.gz qemu-c6cc866c0eaab1deddea21bf0b386730ed71bb97.tar.xz qemu-c6cc866c0eaab1deddea21bf0b386730ed71bb97.zip | |
mem/cxl_type3: fix GPF DVSEC
The structure is for device dvsec not port dvsec. Change type to fix
this issue.
Signed-off-by: Tong Zhang <t.zhang2@samsung.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220915175853.2902-1-t.zhang2@samsung.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| -rw-r--r-- | hw/mem/cxl_type3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3bf2869573..ada2108fac 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -49,7 +49,7 @@ static void build_dvsecs(CXLType3Dev *ct3d) .phase2_power = 0x33, /* 0x33 miliwatts */ }; cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, - GPF_DEVICE_DVSEC_LENGTH, GPF_PORT_DVSEC, + GPF_DEVICE_DVSEC_LENGTH, GPF_DEVICE_DVSEC, GPF_DEVICE_DVSEC_REVID, dvsec); } |