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| author | Richard Henderson | 2018-08-16 01:31:47 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-10-19 04:46:36 +0200 |
| commit | e6cd4bb59b8154fa00da611200beef7eb4e8ec56 (patch) | |
| tree | 092a1f3d8da6fe618602199eb7af7a6f65aa1950 /accel/tcg/user-exec.c | |
| parent | tcg: Add tlb_index and tlb_entry helpers (diff) | |
| download | qemu-e6cd4bb59b8154fa00da611200beef7eb4e8ec56.tar.gz qemu-e6cd4bb59b8154fa00da611200beef7eb4e8ec56.tar.xz qemu-e6cd4bb59b8154fa00da611200beef7eb4e8ec56.zip | |
tcg: Split CONFIG_ATOMIC128
GCC7+ will no longer advertise support for 16-byte __atomic operations
if only cmpxchg is supported, as for x86_64. Fortunately, x86_64 still
has support for __sync_compare_and_swap_16 and we can make use of that.
AArch64 does not have, nor ever has had such support, so open-code it.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg/user-exec.c')
| -rw-r--r-- | accel/tcg/user-exec.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 26a3ffbba1..cd75829cf2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "translate-all.h" #include "exec/helper-proto.h" +#include "qemu/atomic128.h" #undef EAX #undef ECX @@ -615,7 +616,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* The following is only callable from other helpers, and matches up with the softmmu version. */ -#ifdef CONFIG_ATOMIC128 +#if HAVE_ATOMIC128 || HAVE_CMPXCHG128 #undef EXTRA_ARGS #undef ATOMIC_NAME @@ -628,4 +629,4 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define DATA_SIZE 16 #include "atomic_template.h" -#endif /* CONFIG_ATOMIC128 */ +#endif |