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| author | Leon Alrae | 2016-03-15 10:59:33 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:13:59 +0200 |
| commit | dc520a7dee0a9307e844eb6c5d4b21482bf52fcd (patch) | |
| tree | 631041c0e4e82fcd55f2493bca48aa2278b60758 /default-configs/mips-softmmu-common.mak | |
| parent | hw/mips_malta: remove CPUMIPSState from the write_bootloader() (diff) | |
| download | qemu-dc520a7dee0a9307e844eb6c5d4b21482bf52fcd.tar.gz qemu-dc520a7dee0a9307e844eb6c5d4b21482bf52fcd.tar.xz qemu-dc520a7dee0a9307e844eb6c5d4b21482bf52fcd.zip | |
hw/mips_malta: remove redundant irq and clock init
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.
These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'default-configs/mips-softmmu-common.mak')
0 files changed, 0 insertions, 0 deletions