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author | Anthony Liguori | 2012-07-09 18:57:34 +0200 |
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committer | Anthony Liguori | 2012-07-09 18:57:34 +0200 |
commit | 3f6e9a5fad982713440c636f5f7b786e1cc86ca2 (patch) | |
tree | ff7b9b9d8400e4fa6f708681d12991c40c8a7d40 /exec.c | |
parent | Merge remote-tracking branch 'kiszka/queues/slirp' into staging (diff) | |
parent | Maintain the number of dirty pages (diff) | |
download | qemu-3f6e9a5fad982713440c636f5f7b786e1cc86ca2.tar.gz qemu-3f6e9a5fad982713440c636f5f7b786e1cc86ca2.tar.xz qemu-3f6e9a5fad982713440c636f5f7b786e1cc86ca2.zip |
Merge remote-tracking branch 'quintela/migration-anthony-v2' into staging
* quintela/migration-anthony-v2:
Maintain the number of dirty pages
dirty bitmap: abstract its use
Exit loop if we have been there too long
Only calculate expected_time for stage 2
Only TCG needs TLB handling
No need to iterate if we already are over the limit
Add tracepoints for savevm section start/end
Add spent time for migration
Add migration_end function
Add debugging infrastructure
Add save_block_hdr function
Add MigrationParams structure
Add missing check for host_from_stream_offset return value for RAM_SAVE_FLAG_PAGE
Diffstat (limited to 'exec.c')
-rw-r--r-- | exec.c | 34 |
1 files changed, 22 insertions, 12 deletions
@@ -1824,11 +1824,29 @@ void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); } +static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end, + uintptr_t length) +{ + uintptr_t start1; + + /* we modify the TLB cache so that the dirty bit will be set again + when accessing the range */ + start1 = (uintptr_t)qemu_safe_ram_ptr(start); + /* Check that we don't span multiple blocks - this breaks the + address comparisons below. */ + if ((uintptr_t)qemu_safe_ram_ptr(end - 1) - start1 + != (end - 1) - start) { + abort(); + } + cpu_tlb_reset_dirty_all(start1, length); + +} + /* Note: start and end must be within the same ram block. */ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, int dirty_flags) { - uintptr_t length, start1; + uintptr_t length; start &= TARGET_PAGE_MASK; end = TARGET_PAGE_ALIGN(end); @@ -1838,16 +1856,9 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, return; cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); - /* we modify the TLB cache so that the dirty bit will be set again - when accessing the range */ - start1 = (uintptr_t)qemu_safe_ram_ptr(start); - /* Check that we don't span multiple blocks - this breaks the - address comparisons below. */ - if ((uintptr_t)qemu_safe_ram_ptr(end - 1) - start1 - != (end - 1) - start) { - abort(); + if (tcg_enabled()) { + tlb_reset_dirty_range_all(start, end, length); } - cpu_tlb_reset_dirty_all(start1, length); } int cpu_physical_memory_set_dirty_tracking(int enable) @@ -2554,8 +2565,7 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, last_ram_offset() >> TARGET_PAGE_BITS); - memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), - 0xff, size >> TARGET_PAGE_BITS); + cpu_physical_memory_set_dirty_range(new_block->offset, size, 0xff); if (kvm_enabled()) kvm_setup_guest_memory(new_block->host, size); |