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authorPeter Maydell2022-07-15 12:33:39 +0200
committerPeter Maydell2022-07-15 12:33:39 +0200
commit44bfcf628b1531f11ecc21ae96d025a238e1083f (patch)
tree8358899566ea8d4ebd646486ad8fce958f477c1b /hw/arm/aspeed.c
parentMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (diff)
parentaspeed: Add fby35-bmc slot GPIO's (diff)
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Merge tag 'pull-aspeed-20220714' of https://github.com/legoater/qemu into staging
aspeed queue: * New ISL69259 device model * New fby35 multi-SoC machine (AST1030 BIC + AST2600 BMC) * Aspeed GPIO fixes * Extension of m25p80 with write protect bits * More avocado tests using the Aspeed SDK # gpg: Signature made Thu 14 Jul 2022 15:28:09 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20220714' of https://github.com/legoater/qemu: aspeed: Add fby35-bmc slot GPIO's hw/gpio/aspeed: Don't let guests modify input pins qtest/aspeed_gpio: Add input pin modification test hw: m25p80: add tests for BP and TB bit write protect hw: m25p80: Add Block Protect and Top Bottom bits for write protect test/avocado/machine_aspeed.py: Add SDK tests docs: aspeed: Minor updates docs: aspeed: Add fby35 multi-SoC machine section aspeed: Add AST1030 (BIC) to fby35 aspeed: fby35: Add a bootrom for the BMC aspeed: Add AST2600 (BMC) to fby35 aspeed: Add fby35 skeleton aspeed: Make aspeed_board_init_flashes public aspeed: Refactor UART init for multi-SoC machines aspeed: Create SRAM name from first CPU index hw/sensor: Add Renesas ISL69259 device model hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators hw/i2c/pmbus: Add idle state to return 0xff's aspeed: sbc: Allow per-machine settings Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
-rw-r--r--hw/arm/aspeed.c38
1 files changed, 32 insertions, 6 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3340187132..4193a3d23d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -26,6 +26,7 @@
#include "qemu/error-report.h"
#include "qemu/units.h"
#include "hw/qdev-clock.h"
+#include "sysemu/sysemu.h"
static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
@@ -261,7 +262,7 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
}
-static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
+void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
unsigned int count, int unit0)
{
int i;
@@ -301,6 +302,21 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
&error_fatal);
}
+static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
+{
+ AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
+ AspeedSoCState *s = &bmc->soc;
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
+ for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+ if (uart == amc->uart_default) {
+ continue;
+ }
+ aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
+ }
+}
+
static void aspeed_machine_init(MachineState *machine)
{
AspeedMachineState *bmc = ASPEED_MACHINE(machine);
@@ -346,8 +362,7 @@ static void aspeed_machine_init(MachineState *machine)
object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
ASPEED_SCU_PROT_KEY, &error_abort);
}
- qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
- amc->uart_default);
+ connect_serial_hds_to_uarts(bmc);
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
aspeed_board_init_flashes(&bmc->soc.fmc,
@@ -1343,11 +1358,23 @@ static void fby35_reset(MachineState *state)
qemu_devices_reset();
- /* Board ID */
+ /* Board ID: 7 (Class-1, 4 slots) */
object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
+
+ /* Slot presence pins, inverse polarity. (False means present) */
+ object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
+
+ /* Slot 12v power pins, normal polarity. (True means powered-on) */
+ object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
}
static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
@@ -1383,8 +1410,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
object_property_set_link(OBJECT(&bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
- qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
- amc->uart_default);
+ connect_serial_hds_to_uarts(bmc);
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
aspeed_board_init_flashes(&bmc->soc.fmc,