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author | Peter Maydell | 2016-10-24 20:37:33 +0200 |
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committer | Peter Maydell | 2016-10-24 20:37:34 +0200 |
commit | fe4c04071f702e008da7db06d0a220b27e1ab3ac (patch) | |
tree | 97c3699d2cd15ec48436d53218178b903389f6e3 /hw/arm/strongarm.c | |
parent | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (diff) | |
parent | i2c: Add asserts for second smbus i2c_start_transfer() (diff) | |
download | qemu-fe4c04071f702e008da7db06d0a220b27e1ab3ac.tar.gz qemu-fe4c04071f702e008da7db06d0a220b27e1ab3ac.tar.xz qemu-fe4c04071f702e008da7db06d0a220b27e1ab3ac.zip |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161024' into staging
target-arm queue:
* support variable (runtime-determined) page sizes, for a
nearly-20% speedup of TCG for ARMv7 and v8 CPUs with 4K pages
* ptimer: add tests, support more flexible behaviour around
what happens on the "zero" tick, use ptimer for a9gtimer
* virt: ACPI: Add IORT Structure definition
* i2c: Fix SMBus read transactions to avoid double events
* timer: stm32f2xx_timer: add check for prescaler value
* QOMify musicpal, pxa2xx_gpio, strongarm, pl110
* target-arm: Implement new HLT trap for semihosting
* i2c: Add asserts for second smbus i2c_start_transfer()
# gpg: Signature made Mon 24 Oct 2016 18:24:17 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161024: (32 commits)
i2c: Add asserts for second smbus i2c_start_transfer()
target-arm: Implement new HLT trap for semihosting
hw/display: QOM'ify pl110.c
hw/arm: QOM'ify strongarm.c
hw/arm: QOM'ify pxa2xx_gpio.c
hw/arm: QOM'ify musicpal.c
timer: stm32f2xx_timer: add check for prescaler value
i2c: Fix SMBus read transactions to avoid double events
timer: a9gtimer: remove loop to auto-increment comparator
ARM: Virt: ACPI: Build an IORT table with RC and ITS nodes
ACPI: Add IORT Structure definition
tests: Add tests for the ARM MPTimer
arm_mptimer: Convert to use ptimer
tests: ptimer: Replace 10000 with 1
tests: ptimer: Change the copyright comment
tests: ptimer: Add tests for "no counter round down" policy
hw/ptimer: Add "no counter round down" policy
tests: ptimer: Add tests for "no immediate reload" policy
hw/ptimer: Add "no immediate reload" policy
tests: ptimer: Add tests for "no immediate trigger" policy
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/strongarm.c')
-rw-r--r-- | hw/arm/strongarm.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 85db1e2813..3311cc38a4 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1236,6 +1236,11 @@ static void strongarm_uart_init(Object *obj) s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); +} + +static void strongarm_uart_realize(DeviceState *dev, Error **errp) +{ + StrongARMUARTState *s = STRONGARM_UART(dev); qemu_chr_fe_set_handlers(&s->chr, strongarm_uart_can_receive, @@ -1316,6 +1321,7 @@ static void strongarm_uart_class_init(ObjectClass *klass, void *data) dc->reset = strongarm_uart_reset; dc->vmsd = &vmstate_strongarm_uart_regs; dc->props = strongarm_uart_properties; + dc->realize = strongarm_uart_realize; } static const TypeInfo strongarm_uart_info = { @@ -1516,19 +1522,19 @@ static int strongarm_ssp_post_load(void *opaque, int version_id) return 0; } -static int strongarm_ssp_init(SysBusDevice *sbd) +static void strongarm_ssp_init(Object *obj) { + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); DeviceState *dev = DEVICE(sbd); StrongARMSSPState *s = STRONGARM_SSP(dev); sysbus_init_irq(sbd, &s->irq); - memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s, + memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, "ssp", 0x1000); sysbus_init_mmio(sbd, &s->iomem); s->bus = ssi_create_bus(dev, "ssi"); - return 0; } static void strongarm_ssp_reset(DeviceState *dev) @@ -1558,9 +1564,7 @@ static const VMStateDescription vmstate_strongarm_ssp_regs = { static void strongarm_ssp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = strongarm_ssp_init; dc->desc = "StrongARM SSP controller"; dc->reset = strongarm_ssp_reset; dc->vmsd = &vmstate_strongarm_ssp_regs; @@ -1570,6 +1574,7 @@ static const TypeInfo strongarm_ssp_info = { .name = TYPE_STRONGARM_SSP, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(StrongARMSSPState), + .instance_init = strongarm_ssp_init, .class_init = strongarm_ssp_class_init, }; |