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| author | Alistair Francis | 2020-12-15 02:56:54 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | d31e970a01e7399b9cd43ec0dc00c857d968987e (patch) | |
| tree | f7e62273c6e9697bd2cc28a88e4aad8ef21adc69 /hw/char/xilinx_uartlite.c | |
| parent | hw/riscv: Use the CPU to determine if 32-bit (diff) | |
| download | qemu-d31e970a01e7399b9cd43ec0dc00c857d968987e.tar.gz qemu-d31e970a01e7399b9cd43ec0dc00c857d968987e.tar.xz qemu-d31e970a01e7399b9cd43ec0dc00c857d968987e.zip | |
riscv/opentitan: Update the OpenTitan memory layout
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/char/xilinx_uartlite.c')
0 files changed, 0 insertions, 0 deletions