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| author | Daniel Sangorrin | 2012-12-11 12:30:38 +0100 |
|---|---|---|
| committer | Peter Maydell | 2012-12-11 12:30:38 +0100 |
| commit | f47b48fb678581d6ee369cfe26b3513100b7d53e (patch) | |
| tree | ef033c1a0378a9333b650020b622e6f4d18cc5b9 /hw/ds1338.c | |
| parent | xilinx_zynq: Add one variable to avoid overwriting QSPI bus (diff) | |
| download | qemu-f47b48fb678581d6ee369cfe26b3513100b7d53e.tar.gz qemu-f47b48fb678581d6ee369cfe26b3513100b7d53e.tar.xz qemu-f47b48fb678581d6ee369cfe26b3513100b7d53e.zip | |
hw/arm_gic: fix target CPUs affected by set enable/pending ops
Fix a bug on the ARM GIC model where interrupts are not
set pending on the correct target CPUs when they are
triggered by writes to the Interrupt Set Enable or
Set Pending registers.
Signed-off-by: Daniel Sangorrin <dsl@ertl.jp>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ds1338.c')
0 files changed, 0 insertions, 0 deletions