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| author | Zong Li | 2020-07-21 14:40:50 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-22 18:41:36 +0200 |
| commit | 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d (patch) | |
| tree | 59305b59b5488a7b769ea4f0a39b6c92be979dbb /hw/i386/intel_iommu.c | |
| parent | hw/riscv: sifive_e: Correct debug block size (diff) | |
| download | qemu-8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d.tar.gz qemu-8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d.tar.xz qemu-8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d.zip | |
target/riscv: Fix the range of pmpcfg of CSR funcion table
The range of Physical Memory Protection should be from CSR_PMPCFG0
to CSR_PMPCFG3, not to CSR_PMPADDR9.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/i386/intel_iommu.c')
0 files changed, 0 insertions, 0 deletions