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| author | Peter Xu | 2016-07-14 07:56:23 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2016-07-21 19:43:49 +0200 |
| commit | cb135f59b8059c3a372652377ef92fa4a49ad550 (patch) | |
| tree | 244cb6772ba2773c137cc781d96375083f381d89 /hw/i386/pc.c | |
| parent | intel_iommu: get rid of {0} initializers (diff) | |
| download | qemu-cb135f59b8059c3a372652377ef92fa4a49ad550.tar.gz qemu-cb135f59b8059c3a372652377ef92fa4a49ad550.tar.xz qemu-cb135f59b8059c3a372652377ef92fa4a49ad550.zip | |
q35: ioapic: add support for emulated IOAPIC IR
This patch translates all IOAPIC interrupts into MSI ones. One pseudo
ioapic address space is added to transfer the MSI message. By default,
it will be system memory address space. When IR is enabled, it will be
IOMMU address space.
Currently, only emulated IOAPIC is supported.
Idea suggested by Jan Kiszka and Rita Sinha in the following patch:
https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/pc.c')
| -rw-r--r-- | hw/i386/pc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 719884ff88..979f36d99f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1475,6 +1475,9 @@ void pc_memory_init(PCMachineState *pcms, rom_add_option(option_rom[i].name, option_rom[i].bootindex); } pcms->fw_cfg = fw_cfg; + + /* Init default IOAPIC address space */ + pcms->ioapic_as = &address_space_memory; } qemu_irq pc_allocate_cpu_irq(void) |