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| author | Anup Patel | 2022-02-04 18:46:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-02-16 03:24:19 +0100 |
| commit | ac4b0302b0ca986a759538f453b44037c7b66dd9 (patch) | |
| tree | ef7311e05b51711e5b3136eef78298a3af85dff1 /hw/intc/riscv_aplic.c | |
| parent | target/riscv: Implement AIA xiselect and xireg CSRs (diff) | |
| download | qemu-ac4b0302b0ca986a759538f453b44037c7b66dd9.tar.gz qemu-ac4b0302b0ca986a759538f453b44037c7b66dd9.tar.xz qemu-ac4b0302b0ca986a759538f453b44037c7b66dd9.zip | |
target/riscv: Implement AIA IMSIC interface CSRs
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions