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| author | Alistair Francis | 2021-04-01 17:17:57 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:06 +0200 |
| commit | 605def6eeee5e4b6293963aa86be6e637e48bfb3 (patch) | |
| tree | c17daba427c4ef6341109eeb2f3acd7515496aff /hw/intc/xics.c | |
| parent | target/riscv: Fix 32-bit HS mode access permissions (diff) | |
| download | qemu-605def6eeee5e4b6293963aa86be6e637e48bfb3.tar.gz qemu-605def6eeee5e4b6293963aa86be6e637e48bfb3.tar.xz qemu-605def6eeee5e4b6293963aa86be6e637e48bfb3.zip | |
target/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/intc/xics.c')
0 files changed, 0 insertions, 0 deletions