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| author | Alistair Francis | 2021-04-01 17:17:48 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:06 +0200 |
| commit | d6f20dacea5147a9136ec3ecc7124440c16ba862 (patch) | |
| tree | 9ff8d89c91751b603ac3d74459be1e50f6931b25 /hw/intc/xics.c | |
| parent | target/riscv: Use the RISCVException enum for CSR predicates (diff) | |
| download | qemu-d6f20dacea5147a9136ec3ecc7124440c16ba862.tar.gz qemu-d6f20dacea5147a9136ec3ecc7124440c16ba862.tar.xz qemu-d6f20dacea5147a9136ec3ecc7124440c16ba862.zip | |
target/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/intc/xics.c')
0 files changed, 0 insertions, 0 deletions