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| author | Anup Patel | 2022-02-04 18:46:53 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-02-16 03:24:19 +0100 |
| commit | 91870b510ae5d1cb9688231b8f01dceaab64de68 (patch) | |
| tree | ba65ce0852fb058178a1cdd33194cf1879276718 /hw/intc | |
| parent | hw/riscv: virt: Use AIA INTC compatible string when available (diff) | |
| download | qemu-91870b510ae5d1cb9688231b8f01dceaab64de68.tar.gz qemu-91870b510ae5d1cb9688231b8f01dceaab64de68.tar.xz qemu-91870b510ae5d1cb9688231b8f01dceaab64de68.zip | |
target/riscv: Allow users to force enable AIA CSRs in HART
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc')
0 files changed, 0 insertions, 0 deletions