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author | Andreas Färber | 2013-01-10 21:52:28 +0100 |
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committer | Andreas Färber | 2013-01-10 21:52:28 +0100 |
commit | 63e3555e80c31776285accbb4d0c14ae91c457dc (patch) | |
tree | 89907c82724d6519c8bbad7acc15c0198c6f902f /hw/lsi53c895a.c | |
parent | prep: Use pc87312 device instead of collection of random ISA devices (diff) | |
parent | Merge remote-tracking branch 'kraxel/build.1' into staging (diff) | |
download | qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.gz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.xz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.zip |
Merge branch 'master' of git://git.qemu.org/qemu into prep-up
Conflicts:
hw/Makefile.objs
hw/ppc_prep.c
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Diffstat (limited to 'hw/lsi53c895a.c')
-rw-r--r-- | hw/lsi53c895a.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c index 34afe96742..0aafb00b58 100644 --- a/hw/lsi53c895a.c +++ b/hw/lsi53c895a.c @@ -13,9 +13,9 @@ #include <assert.h> #include "hw.h" -#include "pci.h" +#include "pci/pci.h" #include "scsi.h" -#include "dma.h" +#include "sysemu/dma.h" //#define DEBUG_LSI //#define DEBUG_LSI_REG @@ -1878,7 +1878,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) #undef CASE_SET_REG32 } -static void lsi_mmio_write(void *opaque, target_phys_addr_t addr, +static void lsi_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { LSIState *s = opaque; @@ -1886,7 +1886,7 @@ static void lsi_mmio_write(void *opaque, target_phys_addr_t addr, lsi_reg_writeb(s, addr & 0xff, val); } -static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr, +static uint64_t lsi_mmio_read(void *opaque, hwaddr addr, unsigned size) { LSIState *s = opaque; @@ -1904,7 +1904,7 @@ static const MemoryRegionOps lsi_mmio_ops = { }, }; -static void lsi_ram_write(void *opaque, target_phys_addr_t addr, +static void lsi_ram_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { LSIState *s = opaque; @@ -1920,7 +1920,7 @@ static void lsi_ram_write(void *opaque, target_phys_addr_t addr, s->script_ram[addr >> 2] = newval; } -static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr, +static uint64_t lsi_ram_read(void *opaque, hwaddr addr, unsigned size) { LSIState *s = opaque; @@ -1939,14 +1939,14 @@ static const MemoryRegionOps lsi_ram_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static uint64_t lsi_io_read(void *opaque, target_phys_addr_t addr, +static uint64_t lsi_io_read(void *opaque, hwaddr addr, unsigned size) { LSIState *s = opaque; return lsi_reg_readb(s, addr & 0xff); } -static void lsi_io_write(void *opaque, target_phys_addr_t addr, +static void lsi_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { LSIState *s = opaque; |