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| author | Peter Maydell | 2011-08-28 18:22:19 +0200 |
|---|---|---|
| committer | Peter Maydell | 2011-08-28 18:37:12 +0200 |
| commit | 2a952feb8393209634d31d546e202d916e09da06 (patch) | |
| tree | 653697c56149cb637669c32d20b3d210046f230c /hw/omap.h | |
| parent | omap_gpmc: Reindent misindented switch statements (diff) | |
| download | qemu-2a952feb8393209634d31d546e202d916e09da06.tar.gz qemu-2a952feb8393209634d31d546e202d916e09da06.tar.xz qemu-2a952feb8393209634d31d546e202d916e09da06.zip | |
omap_gpmc: Support NAND devices
Support accesses to NAND devices, both by mapping them into
the GPMC address space, and via the NAND_COMMAND, NAND_ADDRESS
and NAND_DATA GPMC registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/omap.h')
| -rw-r--r-- | hw/omap.h | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -122,6 +122,7 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, target_phys_addr_t base, qemu_irq irq); void omap_gpmc_reset(struct omap_gpmc_s *s); void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); +void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); /* * Common IRQ numbers for level 1 interrupt handler |