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author | Anthony Liguori | 2011-05-12 15:08:12 +0200 |
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committer | Anthony Liguori | 2011-05-12 15:08:12 +0200 |
commit | 711c21280b2cb56060859cc574221a8bf40f908a (patch) | |
tree | 9f5385c53ac50e613ae34d4165d02460ef993f0f /hw/pl031.c | |
parent | Merge remote-tracking branch 'agraf/xen-next' into staging (diff) | |
parent | lsi53c895a: Rename 'sense' to 'status' (diff) | |
download | qemu-711c21280b2cb56060859cc574221a8bf40f908a.tar.gz qemu-711c21280b2cb56060859cc574221a8bf40f908a.tar.xz qemu-711c21280b2cb56060859cc574221a8bf40f908a.zip |
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
Conflicts:
cpu-all.h
Diffstat (limited to 'hw/pl031.c')
-rw-r--r-- | hw/pl031.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/pl031.c b/hw/pl031.c index 8c2f9d0bc7..017a313fda 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -161,7 +161,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset, pl031_update(s); break; case RTC_ICR: - /* The PL031 documentation (DDI0224B) states that the interupt is + /* The PL031 documentation (DDI0224B) states that the interrupt is cleared when bit 0 of the written value is set. However the arm926e documentation (DDI0287B) states that the interrupt is cleared when any value is written. */ |