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authorAlistair Francis2021-03-31 17:00:11 +0200
committerAlistair Francis2021-05-11 12:02:06 +0200
commitd4cad544992225105d88c3d744bce1b08947dd24 (patch)
tree64fbfe4e098d81844b0d22bc4b0e7fb71a2211c8 /hw/riscv/opentitan.c
parentMAINTAINERS: Update the RISC-V CPU Maintainers (diff)
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hw/opentitan: Update the interrupt layout
Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/opentitan.c')
-rw-r--r--hw/riscv/opentitan.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index dc9dea117e..557d73726b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_WATERMARK_IRQ));
+ IBEX_UART0_TX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_WATERMARK_IRQ));
+ IBEX_UART0_RX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_EMPTY_IRQ));
+ IBEX_UART0_TX_EMPTY_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_OVERFLOW_IRQ));
+ IBEX_UART0_RX_OVERFLOW_IRQ));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);