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| author | Andreas Färber | 2013-01-10 21:52:28 +0100 |
|---|---|---|
| committer | Andreas Färber | 2013-01-10 21:52:28 +0100 |
| commit | 63e3555e80c31776285accbb4d0c14ae91c457dc (patch) | |
| tree | 89907c82724d6519c8bbad7acc15c0198c6f902f /hw/sh_timer.c | |
| parent | prep: Use pc87312 device instead of collection of random ISA devices (diff) | |
| parent | Merge remote-tracking branch 'kraxel/build.1' into staging (diff) | |
| download | qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.gz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.xz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.zip | |
Merge branch 'master' of git://git.qemu.org/qemu into prep-up
Conflicts:
hw/Makefile.objs
hw/ppc_prep.c
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Diffstat (limited to 'hw/sh_timer.c')
| -rw-r--r-- | hw/sh_timer.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/hw/sh_timer.c b/hw/sh_timer.c index 64bf604ba4..64ea23fce6 100644 --- a/hw/sh_timer.c +++ b/hw/sh_timer.c @@ -10,8 +10,8 @@ #include "hw.h" #include "sh.h" -#include "qemu-timer.h" -#include "exec-memory.h" +#include "qemu/timer.h" +#include "exec/address-spaces.h" #include "ptimer.h" //#define DEBUG_TIMER @@ -59,7 +59,7 @@ static void sh_timer_update(sh_timer_state *s) s->int_level = new_level; } -static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) +static uint32_t sh_timer_read(void *opaque, hwaddr offset) { sh_timer_state *s = (sh_timer_state *)opaque; @@ -79,7 +79,7 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) } } -static void sh_timer_write(void *opaque, target_phys_addr_t offset, +static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) { sh_timer_state *s = (sh_timer_state *)opaque; @@ -222,7 +222,7 @@ typedef struct { int feat; } tmu012_state; -static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset, +static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) { tmu012_state *s = (tmu012_state *)opaque; @@ -253,7 +253,7 @@ static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset, return 0; } -static void tmu012_write(void *opaque, target_phys_addr_t offset, +static void tmu012_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { tmu012_state *s = (tmu012_state *)opaque; @@ -303,7 +303,7 @@ static const MemoryRegionOps tmu012_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base, +void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1) |