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| author | Blue Swirl | 2013-01-26 15:18:28 +0100 |
|---|---|---|
| committer | Blue Swirl | 2013-01-26 15:18:28 +0100 |
| commit | 13144781d4e9e6100b398213f9000576a3dc88f9 (patch) | |
| tree | 9931a5ec29fbc52c69d20c71db970b4c0cfd4a6d /hw/spapr_pci.h | |
| parent | tests: Add gcov support for x86_64 qtest (diff) | |
| parent | PPC: e500: Select MPIC v4.2 on ppce500 platform (diff) | |
| download | qemu-13144781d4e9e6100b398213f9000576a3dc88f9.tar.gz qemu-13144781d4e9e6100b398213f9000576a3dc88f9.tar.xz qemu-13144781d4e9e6100b398213f9000576a3dc88f9.zip | |
Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf:
PPC: e500: Select MPIC v4.2 on ppce500 platform
PPC: e500: fix mpic_iack address
openpic: add basic support for MPIC v4.2
openpic: fix timer address decoding
openpic: fix remaining issues from idr-to-destmask conversion
pseries: Adjust default VIO address allocations to play better with libvirt
pseries: Improve handling of multiple PCI host bridges
target-ppc: Give a meaningful error if too many threads are specified
cuda: Move ADB bus into CUDA state
adb: QOM'ify ADB devices
adb: QOM'ify Apple Desktop Bus
cuda: QOM'ify CUDA
ide/macio: QOM'ify MacIO IDE
mac_nvram: QOM'ify MacIO NVRAM
mac_nvram: Mark as Big Endian
mac_nvram: Clean up public API
macio: Split MacIO in two
macio: Delay qdev init until all fields are initialized
macio: QOM'ify some more
ppc: Move Mac machines to hw/ppc/
Diffstat (limited to 'hw/spapr_pci.h')
| -rw-r--r-- | hw/spapr_pci.h | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h index 7b26ba1561..8bb3c62c3d 100644 --- a/hw/spapr_pci.h +++ b/hw/spapr_pci.h @@ -37,6 +37,7 @@ typedef struct sPAPRPHBState { PCIHostState parent_obj; + int32_t index; uint64_t buid; char *busname; char *dtbusname; @@ -64,18 +65,25 @@ typedef struct sPAPRPHBState { QLIST_ENTRY(sPAPRPHBState) list; } sPAPRPHBState; +#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL + +#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL +#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL +#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 +#define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000 +#define SPAPR_PCI_IO_WIN_OFF 0x80000000 +#define SPAPR_PCI_IO_WIN_SIZE 0x10000 +#define SPAPR_PCI_MSI_WIN_OFF 0x90000000 + +#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL + static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) { return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); } -#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL -#define SPAPR_PCI_IO_WIN_SIZE 0x10000 - -void spapr_create_phb(sPAPREnvironment *spapr, - const char *busname, uint64_t buid, - uint64_t mem_win_addr, uint64_t mem_win_size, - uint64_t io_win_addr, uint64_t msi_win_addr); +PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index, + const char *busname); int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, |