diff options
author | Andreas Färber | 2013-01-10 21:52:28 +0100 |
---|---|---|
committer | Andreas Färber | 2013-01-10 21:52:28 +0100 |
commit | 63e3555e80c31776285accbb4d0c14ae91c457dc (patch) | |
tree | 89907c82724d6519c8bbad7acc15c0198c6f902f /hw/zynq_slcr.c | |
parent | prep: Use pc87312 device instead of collection of random ISA devices (diff) | |
parent | Merge remote-tracking branch 'kraxel/build.1' into staging (diff) | |
download | qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.gz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.tar.xz qemu-63e3555e80c31776285accbb4d0c14ae91c457dc.zip |
Merge branch 'master' of git://git.qemu.org/qemu into prep-up
Conflicts:
hw/Makefile.objs
hw/ppc_prep.c
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Diffstat (limited to 'hw/zynq_slcr.c')
-rw-r--r-- | hw/zynq_slcr.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c index 4f97575770..143a7cf436 100644 --- a/hw/zynq_slcr.c +++ b/hw/zynq_slcr.c @@ -15,9 +15,9 @@ */ #include "hw.h" -#include "qemu-timer.h" +#include "qemu/timer.h" #include "sysbus.h" -#include "sysemu.h" +#include "sysemu/sysemu.h" #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG #define DB_PRINT(...) do { \ @@ -91,7 +91,7 @@ typedef enum { typedef enum { PSS, DDDR, - DMAC, + DMAC = 3, USB, GEM, SDIO, @@ -246,7 +246,7 @@ static void zynq_slcr_reset(DeviceState *d) } static inline uint32_t zynq_slcr_read_imp(void *opaque, - target_phys_addr_t offset) + hwaddr offset) { ZynqSLCRState *s = (ZynqSLCRState *)opaque; @@ -329,21 +329,21 @@ static inline uint32_t zynq_slcr_read_imp(void *opaque, } } -static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset, +static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, unsigned size) { uint32_t ret = zynq_slcr_read_imp(opaque, offset); - DB_PRINT("addr: %08x data: %08x\n", offset, ret); + DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret); return ret; } -static void zynq_slcr_write(void *opaque, target_phys_addr_t offset, +static void zynq_slcr_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { ZynqSLCRState *s = (ZynqSLCRState *)opaque; - DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val); + DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val); switch (offset) { case 0x00: /* SCL */ @@ -476,7 +476,8 @@ static void zynq_slcr_write(void *opaque, target_phys_addr_t offset, break; default: bad_reg: - DB_PRINT("Bad register write %x <= %08x\n", (int)offset, val); + DB_PRINT("Bad register write %x <= %08x\n", (int)offset, + (unsigned)val); } } else { DB_PRINT("SCLR registers are locked. Unlock them first\n"); |