Merge tag 'pull-aspeed-20220503' of https://github.com/legoater/qemu into staging

aspeed queue:

* New AST1030 SoC and eval board
* Accumulative mode support for HACE controller
* GPIO fix and unit test
* Clock modeling adjustments for the AST2600
* Dummy eMMC Boot Controller model
* Change of AST2500 EVB and AST2600 EVB flash model (for quad IO)

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# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
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# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220503' of https://github.com/legoater/qemu:
  aspeed/hace: Support AST1030 HACE
  hw/gpio/aspeed_gpio: Fix QOM pin property
  tests/qtest: Add test for Aspeed HACE accumulative mode
  aspeed/hace: Support AST2600 HACE
  aspeed/hace: Support HMAC Key Buffer register.
  hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model
  test/avocado/machine_aspeed.py: Add ast1030 test case
  aspeed: Add an AST1030 eval board
  aspeed/soc : Add AST1030 support
  aspeed/scu: Add AST1030 support
  aspeed/timer: Add AST1030 support
  aspeed/wdt: Add AST1030 support
  aspeed/wdt: Fix ast2500/ast2600 default reload value
  aspeed/smc: Add AST1030 support
  aspeed/adc: Add AST1030 support
  aspeed: Add eMMC Boot Controller stub
  aspeed: sbc: Correct default reset values
  hw: aspeed_scu: Introduce clkin_25Mhz attribute
  hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 7 insertions, 0 deletions

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 94d5ada95f..4f9ce179bf 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -15,9 +15,12 @@
 #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
 #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
 #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
+#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
+
 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
 
 #define ASPEED_HACE_NR_REGS (0x64 >> 2)
+#define ASPEED_HACE_MAX_SG  256 /* max number of entries */
 
 struct AspeedHACEState {
     SysBusDevice parent;
@@ -25,7 +28,10 @@ struct AspeedHACEState {
     MemoryRegion iomem;
     qemu_irq irq;
 
+    struct iovec iov_cache[ASPEED_HACE_MAX_SG];
     uint32_t regs[ASPEED_HACE_NR_REGS];
+    uint32_t total_req_len;
+    uint32_t iov_count;
 
     MemoryRegion *dram_mr;
     AddressSpace dram_as;
@@ -37,6 +43,7 @@ struct AspeedHACEClass {
 
     uint32_t src_mask;
     uint32_t dest_mask;
+    uint32_t key_mask;
     uint32_t hash_mask;
 };