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| author | Joel Stanley | 2018-08-16 15:05:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:29:58 +0200 |
| commit | 33883ce840b291f4f5767aea911b56acae8dfb66 (patch) | |
| tree | f025cdf610d095c2da4563ef86a510dd001d0dc9 /include/hw/misc/aspeed_sdmc.h | |
| parent | aspeed_sdmc: Set 'cache initial sequence' always true (diff) | |
| download | qemu-33883ce840b291f4f5767aea911b56acae8dfb66.tar.gz qemu-33883ce840b291f4f5767aea911b56acae8dfb66.tar.xz qemu-33883ce840b291f4f5767aea911b56acae8dfb66.zip | |
aspeed_sdmc: Init status always idle
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).
This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/aspeed_sdmc.h')
0 files changed, 0 insertions, 0 deletions