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| author | Cédric Le Goater | 2019-09-25 16:32:30 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-10-15 19:09:04 +0200 |
| commit | d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6 (patch) | |
| tree | ffdc43a7753c3b77b0098c960f96395a39836976 /include | |
| parent | aspeed/timer: Introduce an object class per SoC (diff) | |
| download | qemu-d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6.tar.gz qemu-d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6.tar.xz qemu-d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6.zip | |
aspeed/timer: Add support for control register 3
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
The vmstate version is not increased yet because the structure is
modified again in the following patches.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-6-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/timer/aspeed_timer.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h index a791fee276..1e0288ebc4 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState { uint32_t ctrl; uint32_t ctrl2; + uint32_t ctrl3; AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; AspeedSCUState *scu; |