Merge remote-tracking branch 'remotes/xtensa/tags/20180316-xtensa' into staging

target/xtensa linux-user support.

- small cleanup for xtensa registers dumping (-d cpu);
- add support for debugging linux-user process with xtensa-linux-gdb
  (as opposed to xtensa-elf-gdb), which can only access unprivileged
  registers;
- enable MTTCG for target/xtensa;
- cleanup in linux-user/mmap area making sure that it works correctly
  with limited 30-bit-wide user address space;
- import xtensa-specific definitions from the linux kernel,
  conditionalize user-only/softmmu-only code and add handlers for
  signals, exceptions, process/thread creation and core registers dumping.

# gpg: Signature made Fri 16 Mar 2018 16:46:19 GMT
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180316-xtensa:
  MAINTAINERS: fix W: address for xtensa
  qemu-binfmt-conf.sh: add qemu-xtensa
  target/xtensa: add linux-user support
  linux-user: drop unused target_msync function
  linux-user: fix target_mprotect/target_munmap error return values
  linux-user: fix assertion in shmdt
  linux-user: fix mmap/munmap/mprotect/mremap/shmat
  target/xtensa: support MTTCG
  target/xtensa: use correct number of registers in gdbstub
  target/xtensa: mark register windows in the dump
  target/xtensa: dump correct physical registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	linux-user/syscall.c

1 files changed, 49 insertions, 0 deletions

diff --git a/linux-user/xtensa/target_syscall.h b/linux-user/xtensa/target_syscall.h
new file mode 100644
index 0000000000..3866dad849
--- /dev/null
+++ b/linux-user/xtensa/target_syscall.h
@@ -0,0 +1,49 @@
+#ifndef XTENSA_TARGET_SYSCALL_H
+#define XTENSA_TARGET_SYSCALL_H
+
+#define UNAME_MACHINE "xtensa"
+
+#define UNAME_MINIMUM_RELEASE "3.19"
+#define TARGET_CLONE_BACKWARDS
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+typedef uint32_t xtensa_reg_t;
+typedef struct {
+} xtregs_opt_t; /* TODO */
+
+struct target_pt_regs {
+    xtensa_reg_t pc;            /*   4 */
+    xtensa_reg_t ps;            /*   8 */
+    xtensa_reg_t depc;          /*  12 */
+    xtensa_reg_t exccause;      /*  16 */
+    xtensa_reg_t excvaddr;      /*  20 */
+    xtensa_reg_t debugcause;    /*  24 */
+    xtensa_reg_t wmask;         /*  28 */
+    xtensa_reg_t lbeg;          /*  32 */
+    xtensa_reg_t lend;          /*  36 */
+    xtensa_reg_t lcount;        /*  40 */
+    xtensa_reg_t sar;           /*  44 */
+    xtensa_reg_t windowbase;    /*  48 */
+    xtensa_reg_t windowstart;   /*  52 */
+    xtensa_reg_t syscall;       /*  56 */
+    xtensa_reg_t icountlevel;   /*  60 */
+    xtensa_reg_t scompare1;     /*  64 */
+    xtensa_reg_t threadptr;     /*  68 */
+
+    /* Additional configurable registers that are used by the compiler. */
+    xtregs_opt_t xtregs_opt;
+
+    /* Make sure the areg field is 16 bytes aligned. */
+    int align[0] __attribute__ ((aligned(16)));
+
+    /* current register frame.
+     * Note: The ESF for kernel exceptions ends after 16 registers!
+     */
+    xtensa_reg_t areg[16];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE  2
+
+#endif