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authorAlex Bennée2014-08-04 15:41:56 +0200
committerPeter Maydell2014-08-04 15:41:56 +0200
commitdbb1fb277ca12acd577403575aa6a2f119ab79ea (patch)
treef38c52a60d3aaa144d81b913596c246301117709 /scripts/tracetool
parenttarget-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault (diff)
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target-arm: A64: fix TLB flush instructions
According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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