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author | Alex Bennée | 2014-08-04 15:41:56 +0200 |
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committer | Peter Maydell | 2014-08-04 15:41:56 +0200 |
commit | dbb1fb277ca12acd577403575aa6a2f119ab79ea (patch) | |
tree | f38c52a60d3aaa144d81b913596c246301117709 /scripts/tracetool | |
parent | target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault (diff) | |
download | qemu-dbb1fb277ca12acd577403575aa6a2f119ab79ea.tar.gz qemu-dbb1fb277ca12acd577403575aa6a2f119ab79ea.tar.xz qemu-dbb1fb277ca12acd577403575aa6a2f119ab79ea.zip |
target-arm: A64: fix TLB flush instructions
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/tracetool')
0 files changed, 0 insertions, 0 deletions