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| author | Peter Maydell | 2014-02-26 18:20:03 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-02-26 18:20:03 +0100 |
| commit | 5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e (patch) | |
| tree | f3debbb335a49984dc76822281d9da13cae4133a /target-arm/cpu.h | |
| parent | target-arm: Implement AArch64 memory attribute registers (diff) | |
| download | qemu-5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e.tar.gz qemu-5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e.tar.xz qemu-5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e.zip | |
target-arm: Implement AArch64 SCTLR_EL1
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 51fa63497e..74b1122927 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -169,7 +169,7 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint64_t c0_cssel; /* Cache size selection. */ - uint32_t c1_sys; /* System control register. */ + uint64_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ |