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authorPeter Maydell2015-11-24 15:22:37 +0100
committerPeter Maydell2015-11-24 15:22:38 +0100
commitd9636b6c2b533ab43fad8c9f47633debeef94561 (patch)
treeb21a11aa3359041b2a637ac8bc709ea1b7970bff /target-arm/helper.c
parentMerge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ... (diff)
parenttarget-arm/translate-a64.c: Correct unallocated checks for ldst_excl (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151124' into staging
target-arm queue: * fix minimum RAM check warning on xlnx-ep108 * remove unused define from aarch64-linux-user.mak config * don't mask out bits [47:40] in ARMv8 LPAE descriptors * correct unallocated instruction checks for ldst_excl # gpg: Signature made Tue 24 Nov 2015 14:17:10 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20151124: target-arm/translate-a64.c: Correct unallocated checks for ldst_excl target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8 default-configs/aarch64-linux-user.mak: Remove unused define xlnx-ep108: Fix minimum RAM check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
-rw-r--r--target-arm/helper.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4ecae61197..afc4163342 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6642,6 +6642,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
int ap, ns, xn, pxn;
uint32_t el = regime_el(env, mmu_idx);
bool ttbr1_valid = true;
+ uint64_t descaddrmask;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -6831,6 +6832,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
descaddr = extract64(ttbr, 0, 48);
descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
+ /* The address field in the descriptor goes up to bit 39 for ARMv7
+ * but up to bit 47 for ARMv8.
+ */
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ descaddrmask = 0xfffffffff000ULL;
+ } else {
+ descaddrmask = 0xfffffff000ULL;
+ }
+
/* Secure accesses start with the page table in secure memory and
* can be downgraded to non-secure at any step. Non-secure accesses
* remain non-secure. We implement this by just ORing in the NSTable/NS
@@ -6854,7 +6864,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
/* Invalid, or the Reserved level 3 encoding */
goto do_fault;
}
- descaddr = descriptor & 0xfffffff000ULL;
+ descaddr = descriptor & descaddrmask;
if ((descriptor & 2) && (level < 3)) {
/* Table entry. The top five bits are attributes which may