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| author | Edgar E. Iglesias | 2014-05-27 18:09:51 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-05-27 18:09:51 +0200 |
| commit | 68fdb6c5b0b93d6780255d4f82940d7b342079bd (patch) | |
| tree | 00419034e492961431520f5e4714ef293a9a3606 /target-arm | |
| parent | target-arm: Make esr_el1 an array (diff) | |
| download | qemu-68fdb6c5b0b93d6780255d4f82940d7b342079bd.tar.gz qemu-68fdb6c5b0b93d6780255d4f82940d7b342079bd.tar.xz qemu-68fdb6c5b0b93d6780255d4f82940d7b342079bd.zip | |
target-arm: c12_vbar -> vbar_el[]
No functional change.
Preparation for adding EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-9-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 2 | ||||
| -rw-r--r-- | target-arm/helper-a64.c | 2 | ||||
| -rw-r--r-- | target-arm/helper.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a3cf37527b..62d85ff780 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -198,7 +198,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t c12_vbar; /* vector base address register */ + uint64_t vbar_el[2]; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 13c5865192..b8e6d56b3b 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -443,7 +443,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong addr = env->cp15.c12_vbar; + target_ulong addr = env->cp15.vbar_el[1]; int i; if (arm_current_pl(env) == 0) { diff --git a/target-arm/helper.c b/target-arm/helper.c index 6554656baf..eb5a83261b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -681,7 +681,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) */ - env->cp15.c12_vbar = value & ~0x1FULL; + env->cp15.vbar_el[1] = value & ~0x1FULL; } static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -790,7 +790,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, - .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), @@ -3403,7 +3403,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * and is never in monitor mode this feature is always active. * Note: only bits 31:5 are valid. */ - addr += env->cp15.c12_vbar; + addr += env->cp15.vbar_el[1]; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); |