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| author | Yongbok Kim | 2016-03-24 16:49:58 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:14:00 +0200 |
| commit | f6d4dd810983fdf3d1c9fb81838167efef63d1c8 (patch) | |
| tree | f38749caeb52b4c6e6360a6c0bf8ff9bf7325a15 /target-mips/cpu.h | |
| parent | target-mips: use CP0_CHECK for gen_m{f|t}hc0 (diff) | |
| download | qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.tar.gz qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.tar.xz qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.zip | |
target-mips: add MAAR, MAARI register
The MAAR register is a read/write register included in Release 5
of the architecture that defines the accessibility attributes of
physical address regions. In particular, MAAR defines whether an
instruction fetch or data load can speculatively access a memory
region within the physical address bounds specified by MAAR.
As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 67bbb25adf..866924d188 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -165,6 +165,7 @@ typedef struct mips_def_t mips_def_t; #define MIPS_FPU_MAX 1 #define MIPS_DSP_ACC 4 #define MIPS_KSCRATCH_NUM 6 +#define MIPS_MAAR_MAX 16 /* Must be an even number. */ typedef struct TCState TCState; struct TCState { @@ -483,10 +484,13 @@ struct CPUMIPSState { #define CP0C5_SBRI 6 #define CP0C5_MVH 5 #define CP0C5_LLB 4 +#define CP0C5_MRP 3 #define CP0C5_UFR 2 #define CP0C5_NFExists 0 int32_t CP0_Config6; int32_t CP0_Config7; + uint64_t CP0_MAAR[MIPS_MAAR_MAX]; + int32_t CP0_MAARI; /* XXX: Maybe make LLAddr per-TC? */ uint64_t lladdr; target_ulong llval; |