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| author | Peter Crosthwaite | 2012-12-05 07:53:42 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias | 2012-12-05 09:20:36 +0100 |
| commit | d4d230da08918183929c7d6cb54824b391536904 (patch) | |
| tree | 20778c617d57e72f4988c12d7a7bc448108d8361 /target-mips/dsp_helper.c | |
| parent | Open up 1.4 development branch (diff) | |
| download | qemu-d4d230da08918183929c7d6cb54824b391536904.tar.gz qemu-d4d230da08918183929c7d6cb54824b391536904.tar.xz qemu-d4d230da08918183929c7d6cb54824b391536904.zip | |
xilinx_axienet: Implement R_IS behaviour
The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.
Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-mips/dsp_helper.c')
0 files changed, 0 insertions, 0 deletions