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| author | Peter Maydell | 2016-07-12 13:34:41 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-07-12 13:34:41 +0200 |
| commit | 74e1b782b34e280b06a90f61fdbac5a046cbe491 (patch) | |
| tree | 4e707525686a8c338ec5b013189a5f0d586e89a3 /target-mips/machine.c | |
| parent | Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160712-1' into s... (diff) | |
| parent | target-mips: enable 10-bit ASIDs in I6400 CPU (diff) | |
| download | qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.tar.gz qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.tar.xz qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging
MIPS patches 2016-07-12
Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR
# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160712:
target-mips: enable 10-bit ASIDs in I6400 CPU
target-mips: support CP0.Config4.AE bit
target-mips: change ASID type to hold more than 8 bits
target-mips: add ASID mask field and replace magic values
target-mips: replace MIPS64R6-generic with the real I6400 CPU model
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/mips_cpc: make VP correctly start from the reset vector
target-mips: add exception base to MIPS CPU
hw/mips/cps: create GIC block inside CPS
hw/mips: implement Global Interrupt Controller
hw/mips: implement GIC Interval Timer
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/machine.c')
| -rw-r--r-- | target-mips/machine.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target-mips/machine.c b/target-mips/machine.c index 7314cfe8c7..a27f2f156d 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -132,7 +132,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size) qemu_get_betls(f, &v->VPN); qemu_get_be32s(f, &v->PageMask); - qemu_get_8s(f, &v->ASID); + qemu_get_be16s(f, &v->ASID); qemu_get_be16s(f, &flags); v->G = (flags >> 10) & 1; v->C0 = (flags >> 7) & 3; @@ -156,7 +156,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) { r4k_tlb_t *v = pv; - uint8_t asid = v->ASID; + uint16_t asid = v->ASID; uint16_t flags = ((v->EHINV << 15) | (v->RI1 << 14) | (v->RI0 << 13) | @@ -172,7 +172,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) qemu_put_betls(f, &v->VPN); qemu_put_be32s(f, &v->PageMask); - qemu_put_8s(f, &asid); + qemu_put_be16s(f, &asid); qemu_put_be16s(f, &flags); qemu_put_be64s(f, &v->PFN[0]); qemu_put_be64s(f, &v->PFN[1]); @@ -192,8 +192,8 @@ const VMStateInfo vmstate_info_tlb = { const VMStateDescription vmstate_tlb = { .name = "cpu/tlb", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), |