diff options
| author | Yongbok Kim | 2016-03-24 16:49:58 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:14:00 +0200 |
| commit | f6d4dd810983fdf3d1c9fb81838167efef63d1c8 (patch) | |
| tree | f38749caeb52b4c6e6360a6c0bf8ff9bf7325a15 /target-mips/translate_init.c | |
| parent | target-mips: use CP0_CHECK for gen_m{f|t}hc0 (diff) | |
| download | qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.tar.gz qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.tar.xz qemu-f6d4dd810983fdf3d1c9fb81838167efef63d1c8.zip | |
target-mips: add MAAR, MAARI register
The MAAR register is a read/write register included in Release 5
of the architecture that defines the accessibility attributes of
physical address regions. In particular, MAAR defines whether an
instruction fetch or data load can speculatively access a memory
region within the physical address bounds specified by MAAR.
As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index b44df9e5da..5af077d0de 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -411,7 +411,8 @@ static const mips_def_t mips_defs[] = .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | (0x1c << CP0C4_KScrExist), .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | + (1 << CP0C5_MRP), .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), |