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| author | Maciej W. Rozycki | 2014-11-20 12:15:34 +0100 |
|---|---|---|
| committer | Leon Alrae | 2014-12-16 13:45:20 +0100 |
| commit | 1d725ae952a14b30c84b7bc81b218b8ba77dd311 (patch) | |
| tree | 2b41de5acdbf012a5b877817e6a0bf0c5573fd27 /target-mips | |
| parent | target-mips: gdbstub: Clean up FPU register handling (diff) | |
| download | qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.tar.gz qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.tar.xz qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.zip | |
target-mips: Also apply the CP0.Status mask to MTTC0
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/op_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1267ef297c..7e632f6875 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - other->CP0_Status = arg1 & ~0xf1000018; + other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); sync_c0_status(env, other, other_tc); } |