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| author | Maciej W. Rozycki | 2014-11-18 04:20:28 +0100 |
|---|---|---|
| committer | Leon Alrae | 2014-12-16 13:45:20 +0100 |
| commit | 27e1fb13f21e132011673f0a39e17bcc97583633 (patch) | |
| tree | e1b4e99d46085b273fcad5b15a628fe7a71cf072 /target-mips | |
| parent | target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP (diff) | |
| download | qemu-27e1fb13f21e132011673f0a39e17bcc97583633.tar.gz qemu-27e1fb13f21e132011673f0a39e17bcc97583633.tar.xz qemu-27e1fb13f21e132011673f0a39e17bcc97583633.zip | |
target-mips: Output CP0.Config2-5 in the register dump
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 1a275bf099..70da66f958 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19264,6 +19264,10 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, env->CP0_Status, env->CP0_Cause, env->CP0_EPC); cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n", env->CP0_Config0, env->CP0_Config1, env->lladdr); + cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); if (env->hflags & MIPS_HFLAG_FPU) fpu_dump_state(env, f, cpu_fprintf, flags); #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) |