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| author | Peter Maydell | 2017-07-13 11:47:10 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-07-13 11:47:10 +0200 |
| commit | 6e2c46334385c7e295ac883c801c81b4925fb54f (patch) | |
| tree | 44ddadc2d77a47bb95e77fb5b7463792cb2e598c /target/arm/helper.c | |
| parent | Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int... (diff) | |
| parent | target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (diff) | |
| download | qemu-6e2c46334385c7e295ac883c801c81b4925fb54f.tar.gz qemu-6e2c46334385c7e295ac883c801c81b4925fb54f.tar.xz qemu-6e2c46334385c7e295ac883c801c81b4925fb54f.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170711' into staging
target-arm queue:
* v7M: ignore writes to CONTROL.SPSEL from Thread mode
* KVM: Enable in-kernel timers with user space gic
* aspeed: Register all watchdogs
* hw/misc: Add Exynos4210 Pseudo Random Number Generator
# gpg: Signature made Tue 11 Jul 2017 11:28:15 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170711:
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
ARM: KVM: Enable in-kernel timers with user space gic
aspeed: Register all watchdogs
hw/misc: Add Exynos4210 Pseudo Random Number Generator
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 2594faa9b8..4ed32c56b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8768,9 +8768,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 20: /* CONTROL */ - switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); - env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK | - R_V7M_CONTROL_NPRIV_MASK); + /* Writing to the SPSEL bit only has an effect if we are in + * thread mode; other bits can be updated by any privileged code. + * switch_v7m_sp() deals with updating the SPSEL bit in + * env->v7m.control, so we only need update the others. + */ + if (env->v7m.exception == 0) { + switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); + } + env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK; break; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" |