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| author | Richard Henderson | 2019-01-21 11:23:12 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-01-21 11:38:54 +0100 |
| commit | 64be86ab1b5ef10b660a4230ee7f27c0da499043 (patch) | |
| tree | 5c3d3f30702943ceca653af6e9d0fb5eceadc79a /target/arm | |
| parent | target/arm: Introduce arm_mmu_idx (diff) | |
| download | qemu-64be86ab1b5ef10b660a4230ee7f27c0da499043.tar.gz qemu-64be86ab1b5ef10b660a4230ee7f27c0da499043.tar.xz qemu-64be86ab1b5ef10b660a4230ee7f27c0da499043.zip | |
target/arm: Introduce arm_stage1_mmu_idx
While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190108223129.5570-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper.c | 7 | ||||
| -rw-r--r-- | target/arm/internals.h | 15 |
2 files changed, 22 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 36d1832e32..35bbc7f109 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12998,6 +12998,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch) return arm_to_core_mmu_idx(arm_mmu_idx(env)); } +#ifndef CONFIG_USER_ONLY +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return stage_1_mmu_idx(arm_mmu_idx(env)); +} +#endif + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { diff --git a/target/arm/internals.h b/target/arm/internals.h index 89f3b122a4..248fdf7a3c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -927,4 +927,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu); */ ARMMMUIdx arm_mmu_idx(CPUARMState *env); +/** + * arm_stage1_mmu_idx: + * @env: The cpu environment + * + * Return the ARMMMUIdx for the stage1 traversal for the current regime. + */ +#ifdef CONFIG_USER_ONLY +static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return ARMMMUIdx_S1NSE0; +} +#else +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); +#endif + #endif |