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| author | Richard Henderson | 2017-10-09 19:17:24 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-01-30 19:08:18 +0100 |
| commit | 3d68ee7bbe34278d5792f5341ba0246069c6191c (patch) | |
| tree | e3e5dff266fe0eb24e5d6bb0ea75964ee4e3bf52 /target/hppa/cpu.h | |
| parent | target/hppa: Split address size from register size (diff) | |
| download | qemu-3d68ee7bbe34278d5792f5341ba0246069c6191c.tar.gz qemu-3d68ee7bbe34278d5792f5341ba0246069c6191c.tar.xz qemu-3d68ee7bbe34278d5792f5341ba0246069c6191c.zip | |
target/hppa: Implement mmu_idx from IA privilege level
Most aspects of privilege are not yet handled. But this
gives us the start from which to begin checking.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/cpu.h')
| -rw-r--r-- | target/hppa/cpu.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 9fe5ea0a69..f60435b9ec 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,8 +36,10 @@ #define TARGET_PAGE_BITS 12 #define ALIGNED_ONLY -#define NB_MMU_MODES 1 -#define MMU_USER_IDX 0 +#define NB_MMU_MODES 5 +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 /* Hardware exceptions, interupts, faults, and traps. */ @@ -195,7 +197,14 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { - return 0; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return env->iaoq_f & 3; + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif } void hppa_translate_init(void); @@ -210,7 +219,9 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, { *pc = env->iaoq_f; *cs_base = env->iaoq_b; - *pflags = env->psw_n; + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) + | env->psw_n * PSW_N; } target_ureg cpu_hppa_get_psw(CPUHPPAState *env); |