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author | Peter Maydell | 2019-06-10 17:09:19 +0200 |
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committer | Peter Maydell | 2019-06-10 17:09:19 +0200 |
commit | a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (patch) | |
tree | 90697278e6aefd0b91858c403ddb5670f6bdf053 /target/hppa/mem_helper.c | |
parent | Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190607-pull-request' ... (diff) | |
parent | tcg/arm: Remove mostly unreachable tlb special case (diff) | |
download | qemu-a578cdfbdd8f9beff5ced52b7826ddb1669abbbf.tar.gz qemu-a578cdfbdd8f9beff5ced52b7826ddb1669abbbf.tar.xz qemu-a578cdfbdd8f9beff5ced52b7826ddb1669abbbf.zip |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState
# gpg: Signature made Mon 10 Jun 2019 15:07:55 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20190610: (39 commits)
tcg/arm: Remove mostly unreachable tlb special case
tcg/arm: Use LDRD to load tlb mask+table
tcg/aarch64: Use LDP to load tlb mask+table
cpu: Remove CPU_COMMON
cpu: Move the softmmu tlb to CPUNegativeOffsetState
cpu: Move icount_decr to CPUNegativeOffsetState
cpu: Introduce CPUNegativeOffsetState
cpu: Introduce cpu_set_cpustate_pointers
cpu: Move ENV_OFFSET to exec/gen-icount.h
target/xtensa: Use env_cpu, env_archcpu
target/unicore32: Use env_cpu, env_archcpu
target/tricore: Use env_cpu
target/tilegx: Use env_cpu
target/sparc: Use env_cpu, env_archcpu
target/sh4: Use env_cpu, env_archcpu
target/s390x: Use env_cpu, env_archcpu
target/riscv: Use env_cpu, env_archcpu
target/ppc: Use env_cpu, env_archcpu
target/openrisc: Use env_cpu, env_archcpu
target/nios2: Use env_cpu, env_archcpu
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/hppa/mem_helper.c')
-rw-r--r-- | target/hppa/mem_helper.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 0fd3ac6645..b12c5b5054 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -56,7 +56,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) { - CPUState *cs = CPU(hppa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned i, n = 1 << (2 * ent->page_size); uint64_t addr = ent->va_b; @@ -329,7 +329,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) { - CPUState *src = CPU(hppa_env_get_cpu(env)); + CPUState *src = env_cpu(env); CPUState *cpu; trace_hppa_tlb_ptlb(env); run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr); @@ -346,17 +346,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { - CPUState *src = CPU(hppa_env_get_cpu(env)); trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } void cpu_hppa_change_prot_id(CPUHPPAState *env) { if (env->psw & PSW_P) { - CPUState *src = CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } } |