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| author | Yongbok Kim | 2019-01-03 16:46:32 +0100 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-01-18 16:53:28 +0100 |
| commit | 043715d1e0fbb3e3411be3f898c5b77b7f90327a (patch) | |
| tree | 1e92367ebcd199a0e18f4b4233e076299946c440 /target/mips/cpu.h | |
| parent | target/mips: Add field and R/W access to ITU control register ICR0 (diff) | |
| download | qemu-043715d1e0fbb3e3411be3f898c5b77b7f90327a.tar.gz qemu-043715d1e0fbb3e3411be3f898c5b77b7f90327a.tar.xz qemu-043715d1e0fbb3e3411be3f898c5b77b7f90327a.zip | |
target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 185702d1e9..48e86d1ad4 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -326,6 +326,7 @@ struct TCState { }; +struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; @@ -917,6 +918,7 @@ struct CPUMIPSState { const mips_def_t *cpu_model; void *irq[8]; QEMUTimer *timer; /* Internal timer */ + struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ }; @@ -1059,6 +1061,9 @@ void cpu_set_exception_base(int vp_index, target_ulong address); /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); +/* mips_itu.c */ +void itc_reconfigure(struct MIPSITUState *tag); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); |