diff options
| author | Fredrik Noring | 2019-01-17 18:44:05 +0100 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-01-18 16:53:28 +0100 |
| commit | a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd (patch) | |
| tree | 3ce5635f8ee58d3e45ee71d21c1c325d62a7020b /target/mips/cpu.h | |
| parent | target/mips: Rename 'rn' to 'register_name' (diff) | |
| download | qemu-a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd.tar.gz qemu-a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd.tar.xz qemu-a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd.zip | |
target/mips: Introduce 32 R5900 multimedia registers
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21daf501ce..c4da7dfbfd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -429,6 +429,9 @@ struct TCState { float_status msa_fp_status; + /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ + uint64_t mmr[32]; + #define NUMBER_OF_MXU_REGISTERS 16 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; target_ulong mxu_cr; |