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| author | Richard Henderson | 2018-05-23 17:14:46 +0200 |
|---|---|---|
| committer | Stafford Horne | 2018-07-02 17:05:28 +0200 |
| commit | d5cabcce62aeef63afd2b45ec634334df53c70c9 (patch) | |
| tree | 401c60cb2f0f0dadaed208bfd43a34260148f151 /target/openrisc/cpu.c | |
| parent | target/openrisc: Fix mtspr shadow gprs (diff) | |
| download | qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.tar.gz qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.tar.xz qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.zip | |
target/openrisc: Add print_insn_or1k
Rather than emit disassembly while translating, reuse the
generated decoder to build a separate disassembler.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index a692a98ec0..fa8e342ff7 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -35,6 +35,11 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } +static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn = print_insn_or1k; +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -152,6 +157,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->gdb_num_core_regs = 32 + 3; cc->tcg_initialize = openrisc_translate_init; + cc->disas_set_info = openrisc_disas_set_info; } /* Sort alphabetically by type name, except for "any". */ |