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| author | Tim 'mithro' Ansell | 2017-04-18 08:15:50 +0200 |
|---|---|---|
| committer | Stafford Horne | 2017-04-21 16:55:48 +0200 |
| commit | 356a2db3c6f84e8e79e5afa3913514184bff5f50 (patch) | |
| tree | 08c1c57091a126f8834bb6a06f8971304b28959a /target/openrisc/cpu.h | |
| parent | MAINTAINERS: Add myself as openrisc maintainer (diff) | |
| download | qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.tar.gz qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.tar.xz qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.zip | |
target/openrisc: Implement EVBAR register
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6960..1958b72718 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S = (1 << 7), CPUCFGR_OF64S = (1 << 8), CPUCFGR_OV64S = (1 << 9), + /* CPUCFGR_ND = (1 << 10), */ + /* CPUCFGR_AVRP = (1 << 11), */ + CPUCFGR_EVBARP = (1 << 12), + /* CPUCFGR_ISRP = (1 << 13), */ + /* CPUCFGR_AECSRP = (1 << 14), */ }; /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S = (1 << 7), OPENRISC_FEATURE_OF64S = (1 << 8), OPENRISC_FEATURE_OV64S = (1 << 9), + OPENRISC_FEATURE_EVBAR = (1 << 12), }; /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; |