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| author | Richard Henderson | 2018-05-23 17:14:46 +0200 |
|---|---|---|
| committer | Stafford Horne | 2018-07-02 17:05:28 +0200 |
| commit | d5cabcce62aeef63afd2b45ec634334df53c70c9 (patch) | |
| tree | 401c60cb2f0f0dadaed208bfd43a34260148f151 /target/openrisc/cpu.h | |
| parent | target/openrisc: Fix mtspr shadow gprs (diff) | |
| download | qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.tar.gz qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.tar.xz qemu-d5cabcce62aeef63afd2b45ec634334df53c70c9.zip | |
target/openrisc: Add print_insn_or1k
Rather than emit disassembly while translating, reuse the
generated decoder to build a separate disassembler.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 35cab65f11..c871d6bfe1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -358,6 +358,7 @@ void openrisc_translate_init(void); int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); +int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #define cpu_signal_handler cpu_openrisc_signal_handler |