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| author | Michael Clark | 2018-03-04 21:27:28 +0100 |
|---|---|---|
| committer | Alistair Francis | 2018-09-04 22:19:23 +0200 |
| commit | c3b03e5800a7151d3c746f40efceabdfdae08f85 (patch) | |
| tree | 0f9711fffef25b426df4b0b2398b393f5571b68d /target/riscv/cpu_bits.h | |
| parent | RISC-V: Update address bits to support sv39 and sv48 (diff) | |
| download | qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.tar.gz qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.tar.xz qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.zip | |
RISC-V: Improve page table walker spec compliance
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 64aa097181..12b4757088 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -407,5 +407,3 @@ #define PTE_SOFT 0x300 /* Reserved for Software */ #define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) |