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| author | Peter Maydell | 2017-10-25 17:38:57 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-10-25 17:38:57 +0200 |
| commit | ae49fbbcd8e4e9d8bf7131add34773f579e1aff7 (patch) | |
| tree | 5981acc5f85f69062f1e67bef90465295dac25c7 /target/tilegx/translate.c | |
| parent | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20171023' i... (diff) | |
| parent | translate-all: exit from tb_phys_invalidate if qht_remove fails (diff) | |
| download | qemu-ae49fbbcd8e4e9d8bf7131add34773f579e1aff7.tar.gz qemu-ae49fbbcd8e4e9d8bf7131add34773f579e1aff7.tar.xz qemu-ae49fbbcd8e4e9d8bf7131add34773f579e1aff7.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171025' into staging
TCG patch queue
# gpg: Signature made Wed 25 Oct 2017 10:30:18 BST
# gpg: using RSA key 0x64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20171025: (51 commits)
translate-all: exit from tb_phys_invalidate if qht_remove fails
tcg: Initialize cpu_env generically
tcg: enable multiple TCG contexts in softmmu
tcg: introduce regions to split code_gen_buffer
translate-all: use qemu_protect_rwx/none helpers
osdep: introduce qemu_mprotect_rwx/none
tcg: allocate optimizer temps with tcg_malloc
tcg: distribute profiling counters across TCGContext's
tcg: introduce **tcg_ctxs to keep track of all TCGContext's
gen-icount: fold exitreq_label into TCGContext
tcg: define tcg_init_ctx and make tcg_ctx a pointer
tcg: take tb_ctx out of TCGContext
translate-all: report correct avg host TB size
exec-all: rename tb_free to tb_remove
translate-all: use a binary search tree to track TBs in TBContext
tcg: Remove CF_IGNORE_ICOUNT
tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK
cpu-exec: lookup/generate TB outside exclusive region during step_atomic
tcg: check CF_PARALLEL instead of parallel_cpus
target/sparc: check CF_PARALLEL instead of parallel_cpus
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/tilegx/translate.c')
| -rw-r--r-- | target/tilegx/translate.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ace2830a84..d55549dabc 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -33,7 +33,6 @@ #define FMT64X "%016" PRIx64 -static TCGv_env cpu_env; static TCGv cpu_pc; static TCGv cpu_regs[TILEGX_R_COUNT]; @@ -2378,7 +2377,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) uint64_t pc_start = tb->pc; uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; int num_insns = 0; - int max_insns = tb->cflags & CF_COUNT_MASK; + int max_insns = tb_cflags(tb) & CF_COUNT_MASK; dc->pc = pc_start; dc->mmuidx = 0; @@ -2445,8 +2444,6 @@ void tilegx_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc"); for (i = 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] = tcg_global_mem_new_i64(cpu_env, |