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| author | Richard Henderson | 2018-06-27 17:40:23 +0200 |
|---|---|---|
| committer | Stafford Horne | 2018-07-02 15:31:59 +0200 |
| commit | c3513c836e4c19cd7a2a7f691995fdef587cec72 (patch) | |
| tree | b503d5ad3b37a4fa9c85e591af9966c260d2e1e8 /target | |
| parent | tcg: Fix --disable-tcg build breakage (diff) | |
| download | qemu-c3513c836e4c19cd7a2a7f691995fdef587cec72.tar.gz qemu-c3513c836e4c19cd7a2a7f691995fdef587cec72.tar.xz qemu-c3513c836e4c19cd7a2a7f691995fdef587cec72.zip | |
target/openrisc: Fix mtspr shadow gprs
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/openrisc/sys_helper.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b284064381..2f337363ec 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx = (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] = rb; + break; case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); |