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author | Blue Swirl | 2012-09-22 19:59:15 +0200 |
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committer | Blue Swirl | 2012-09-22 19:59:15 +0200 |
commit | 04cbbdeefdda2615b11f7890f1e61b750e83129f (patch) | |
tree | c2426674527ce95eec5ccbf4bf5cae1eec3d7ea0 /tcg/sparc/tcg-target.h | |
parent | target-xtensa: implement coprocessor context option (diff) | |
parent | tcg-sparc: Preserve branch destinations during retranslation (diff) | |
download | qemu-04cbbdeefdda2615b11f7890f1e61b750e83129f.tar.gz qemu-04cbbdeefdda2615b11f7890f1e61b750e83129f.tar.xz qemu-04cbbdeefdda2615b11f7890f1e61b750e83129f.zip |
Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rth
* 'tcg-sparc' of git://repo.or.cz/qemu/rth:
tcg-sparc: Preserve branch destinations during retranslation
tcg-sparc: Fix and enable direct TB chaining.
tcg-sparc: Add %g/%o registers to alloc_order
tcg-sparc: Use defines for temporaries.
tcg-sparc: Mask shift immediates to avoid illegal insns.
tcg-sparc: Clean up cruft stemming from attempts to use global registers.
tcg-sparc: Change AREG0 in generated code to %i0.
tcg-sparc: Support GUEST_BASE.
tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
tcg-sparc: Don't MAP_FIXED on top of the program
tcg-sparc: Fix ADDX opcode.
tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
linux-user: Use memcpy in get_user/put_user.
Diffstat (limited to 'tcg/sparc/tcg-target.h')
-rw-r--r-- | tcg/sparc/tcg-target.h | 33 |
1 files changed, 13 insertions, 20 deletions
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d76257403d..6314ffb303 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -66,22 +66,19 @@ typedef enum { #define TCG_CT_CONST_S13 0x200 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_I6 -#ifdef __arch64__ -// Reserve space for AREG0 -#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \ - TCG_STATIC_CALL_ARGS_SIZE) -#define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16) -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_REG_CALL_STACK TCG_REG_O6 + +#if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_STACK_BIAS 2047 +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #else -// AREG0 + one word for alignment -#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \ - TCG_STATIC_CALL_ARGS_SIZE) -#define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME -#define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_STACK_BIAS 0 +#define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4) #endif -#ifdef __arch64__ +#if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_EXTEND_ARGS 1 #endif @@ -127,13 +124,9 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i64 0 #endif -#ifdef CONFIG_SOLARIS -#define TCG_AREG0 TCG_REG_G2 -#elif defined(__sparc_v9__) -#define TCG_AREG0 TCG_REG_G5 -#else -#define TCG_AREG0 TCG_REG_G6 -#endif +#define TCG_TARGET_HAS_GUEST_BASE + +#define TCG_AREG0 TCG_REG_I0 static inline void flush_icache_range(tcg_target_ulong start, tcg_target_ulong stop) |