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authorMatheus Ferst2022-03-05 07:16:46 +0100
committerCédric Le Goater2022-03-05 07:16:46 +0100
commit63c2b746bebef3ec9de4f29d5beeea4ee809c892 (patch)
tree7db1fa2a7e4e3c9a6ca3a6e0cad939f710586074 /tests
parenttests/tcg/ppc64le: drop __int128 usage in bcdsub (diff)
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tests/tcg/ppc64le: emit bcdsub with .long when needed
Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the absence of other means to detect this support at config-time, we resort to __has_builtin to identify the presence of __builtin_bcdsub at compile-time. If the builtin is not available, the instruction is emitted with a ".long". [1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html [2] https://github.com/llvm/llvm-project/commit/59eb767e11d4ffefb5f55409524e5c8416b2b0db [3] https://github.com/llvm/llvm-project/commit/c933c2eb334660c131f4afc9d194fafb0cec0423 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'tests')
-rw-r--r--tests/tcg/ppc64le/bcdsub.c73
1 files changed, 42 insertions, 31 deletions
diff --git a/tests/tcg/ppc64le/bcdsub.c b/tests/tcg/ppc64le/bcdsub.c
index 12da19b78e..87c8c44a44 100644
--- a/tests/tcg/ppc64le/bcdsub.c
+++ b/tests/tcg/ppc64le/bcdsub.c
@@ -9,37 +9,48 @@
#define CRF_SO (1 << 0)
#define UNDEF 0
-/*
- * Use GPR pairs to load the VSR values and place the resulting VSR and CR6 in
- * th, tl, and cr. Note that we avoid newer instructions (e.g., mtvsrdd/mfvsrld)
- * so we can run this test on POWER8 machines.
- */
-#define BCDSUB(AH, AL, BH, BL, PS) \
- asm ("mtvsrd 32, %3\n\t" \
- "mtvsrd 33, %4\n\t" \
- "xxmrghd 32, 32, 33\n\t" \
- "mtvsrd 33, %5\n\t" \
- "mtvsrd 34, %6\n\t" \
- "xxmrghd 33, 33, 34\n\t" \
- "bcdsub. 0, 0, 1, %7\n\t" \
- "mfocrf %0, 0b10\n\t" \
- "mfvsrd %1, 32\n\t" \
- "xxswapd 32, 32\n\t" \
- "mfvsrd %2, 32\n\t" \
- : "=r" (cr), "=r" (th), "=r" (tl) \
- : "r" (AH), "r" (AL), "r" (BH), "r" (BL), "i" (PS) \
- : "v0", "v1", "v2");
-
-#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
- do { \
- int cr = 0; \
- uint64_t th, tl; \
- BCDSUB(AH, AL, BH, BL, PS); \
- if (TH != UNDEF || TL != UNDEF) { \
- assert(tl == TL); \
- assert(th == TH); \
- } \
- assert((cr >> 4) == CR6); \
+#ifdef __has_builtin
+#if !__has_builtin(__builtin_bcdsub)
+#define NO_BUILTIN_BCDSUB
+#endif
+#endif
+
+#ifdef NO_BUILTIN_BCDSUB
+#define BCDSUB(T, A, B, PS) \
+ ".long 4 << 26 | (" #T ") << 21 | (" #A ") << 16 | (" #B ") << 11" \
+ " | 1 << 10 | (" #PS ") << 9 | 65\n\t"
+#else
+#define BCDSUB(T, A, B, PS) "bcdsub. " #T ", " #A ", " #B ", " #PS "\n\t"
+#endif
+
+#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
+ do { \
+ int cr = 0; \
+ uint64_t th, tl; \
+ /* \
+ * Use GPR pairs to load the VSR values and place the resulting VSR and\
+ * CR6 in th, tl, and cr. Note that we avoid newer instructions (e.g., \
+ * mtvsrdd/mfvsrld) so we can run this test on POWER8 machines. \
+ */ \
+ asm ("mtvsrd 32, %3\n\t" \
+ "mtvsrd 33, %4\n\t" \
+ "xxmrghd 32, 32, 33\n\t" \
+ "mtvsrd 33, %5\n\t" \
+ "mtvsrd 34, %6\n\t" \
+ "xxmrghd 33, 33, 34\n\t" \
+ BCDSUB(0, 0, 1, PS) \
+ "mfocrf %0, 0b10\n\t" \
+ "mfvsrd %1, 32\n\t" \
+ "xxswapd 32, 32\n\t" \
+ "mfvsrd %2, 32\n\t" \
+ : "=r" (cr), "=r" (th), "=r" (tl) \
+ : "r" (AH), "r" (AL), "r" (BH), "r" (BL) \
+ : "v0", "v1", "v2"); \
+ if (TH != UNDEF || TL != UNDEF) { \
+ assert(tl == TL); \
+ assert(th == TH); \
+ } \
+ assert((cr >> 4) == CR6); \
} while (0)
/*